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AD1940
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 32
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
VDD
VDD
MCLK
RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
PLL_VDD
NC
GND
PIN 1
AD1940
TOP VIEW
(Not to Scale)
V
S
S
S
C
C
C
C
R
G
S
A
G
V
V
V
V
I
S
S
O
S
S
V
0
LRCLK_IN
BCLK_IN
NC = NO CONNECT
Figure 6. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
I/O
1, 25, 37
2
IN
3
4
IN
5
IN
6
IN
7
8
9
10
IN
11
IN
12, 24, 36, 48
13
14
IN
15
IN
16
IN
17
IN
18
IN
19
OUT
20
IN
21
IN
22
IN
23
IN
26
IN/OUT
27
IN/OUT
28, 33, 40
29
OUT
30
OUT
Mnemonic
VDD
MCLK
RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
PLL_VDD
NC
LRCLK_IN
BCLK_IN
GND
VDD
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
ADR_SEL
COUT
CCLK
CLATCH
CDATA
RESETB
LRCLK_OUT0
BCLK_OUT0
ODVDD
SDATA_OUT0/TDM_O0
SDATA_OUT1
Description
Core Power.
Master Clock Input.
This pin should be connected to ground.
PLL Control 0.
PLL Control 1.
PLL Control 2.
PLL Ground.
PLL Power.
No Connect.
Left/Right Clock for Serial or TDM Data Inputs.
Bit Clock for Serial or TDM Data Inputs.
Digital Ground.
Core Power.
Serial Data Input 0.
Serial Data Input 1.
Serial Data Input 2/TDM Input 1.
Serial Data Input 3/TDM Input 0.
Control Port Address Select.
SPI Data Output.
SPI Clock.
SPI Data Latch.
SPI Data Input.
Reset the AD1940
Left/Right Clock Output 0.
Bit Clock Output 0.
Power Connection for Output Pins.
Serial Data Output 0/TDM (16- or 8-Channel) Output 0.
Serial Data Output 1.
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